Multistage Interconnection Networks for Multiprocessor Systems

Publisher Summary The chapter provides a survey of multistage interconnection networks (MINs) emphasizing the underlying topological design principles. An MIN consists of a sequence of switching stages, each of which consists of several switches. The switching stages are connected with interstage links between successive stages. The chapter discusses the design parameters of MINs. MIN design consists of three different layers: the network topology, functional characteristics of a switch, and the control strategy. These three layers of MIN design are not independent, they strongly influence each other. The chapter examines four important classes of MINs: non-blocking, re-arrangeable, blocking, and multipath. It deals with the performance analysis and very-large-scale implementation (VLSI) of MINs. Combinatorial power (CP), path blockage (PB), and bandwidth (BW) are discussed as three different measures of performance of a MIN. The omega network is presented as a typical example of a network with digit control. The destination tag algorithm, data-alignment requirement, and routing conflicts for the omega network are discussed.

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