The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors

We offer a solution to the problem of verifying formal memory models of processors by combining the strengths of model-checking and a formal testing procedure for parallel machines. We characterize the formal basis for abstracting the tests into test automata and associated memory rule safety properties whose violations pinpoint the ordering rule being violated. Our experimental results on Verilog models of a commercial split transaction bus demonstrates the ability of our method to effectively debug design models during early stages of their development.

[1]  Leslie Lamport,et al.  The temporal logic of actions , 1994, TOPL.

[2]  Phillip B. Gibbons,et al.  On testing cache-coherent shared memories , 1994, SPAA '94.

[3]  Rob Gerth Sequential consistency and the lazy caching algorithm , 1999, Distributed Computing.

[4]  Leslie Lamport,et al.  How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs , 2016, IEEE Transactions on Computers.

[5]  Robert K. Brayton,et al.  Automatic Datapath Abstraction In Hardware Systems , 1995, CAV.

[6]  E. Clarke,et al.  Automatic Veriication of Nite-state Concurrent Systems Using Temporal-logic Speciications. Acm , 1993 .

[7]  David L. Dill,et al.  Verification of FLASH cache coherence protocol by aggregation of distributed transactions , 1996, SPAA '96.

[8]  David L. Dill,et al.  Formal specification of abstract memory models , 1993 .

[9]  R.K. Brayton,et al.  Automatic verification of memory systems which service their requests out of order , 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

[10]  Albert John Camilleri,et al.  A Hybrid Approach to Verifying Liveness in a Symmetric Multi-Processor , 1997, TPHOLs.

[11]  Ganesh Gopalakrishnan,et al.  Using “test model-checking” to verify the Runway-PA8000 memory model , 1998, SPAA '98.

[12]  Leslie Lamport,et al.  Lazy caching in TLA , 1999, Distributed Computing.

[13]  Sérgio Vale Aguiar Campos,et al.  Symbolic Model Checking , 1993, CAV.

[14]  William R. Bryg,et al.  A High-Performance, Low-Cost Multiprocessor Bus for Workstations and Midrange Servers , 1996 .

[15]  Yehuda Afek,et al.  Lazy caching , 1993, TOPL.

[16]  William W. Collier,et al.  Reasoning about parallel architectures , 1992 .

[17]  Sarita V. Adve,et al.  Shared Memory Consistency Models: A Tutorial , 1996, Computer.

[18]  Rajeev Alur,et al.  Model-checking of correctness conditions for concurrent objects , 1996, Proceedings 11th Annual IEEE Symposium on Logic in Computer Science.

[19]  Leslie Lamport,et al.  How to Make a Correct Multiprocess Program Execute Correctly on a Multiprocessor , 1997, IEEE Trans. Computers.

[20]  David L Weaver,et al.  The SPARC architecture manual : version 9 , 1994 .

[21]  Gerry Kane,et al.  PA-RISC 2.0 Architecture , 1995 .

[22]  Phillip B. Gibbons,et al.  Testing Shared Memories , 1997, SIAM J. Comput..

[23]  Ganesh Gopalakrishnan,et al.  Formal modeling and validation applied to a commercial coherent bus: a case study , 1997, CHARME.

[24]  Susanne Graf,et al.  Verification of a Distributed Cache Memory by Using Abstractions , 1994, CAV.