A nano-CMOS process variation induced read failure tolerant SRAM cell

In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is proposed which is highly stable against nanoscale process variations as well as power efficient. The effectiveness of the proposed cell is exhaustively evaluated through detailed Monte Carlo simulations. It is observed that the 16% variation in threshold voltage results in negligible effects on static noise margin (SNM) during read operation. Experiments under different loading conditions indicate that there is reduction 2X (approximately) in power dissipation and 2X (approximately) in leakage.

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