A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware [multimedia applications]
暂无分享,去创建一个
[1] Rudy Lauwereins,et al. Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[2] Rudy Lauwereins,et al. Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs , 2001, IEEE Des. Test Comput..
[3] Diederik Verkest,et al. A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs , 2004, Microprocess. Microsystems.
[4] Francky Catthoor,et al. Pareto-optimization-based run-time task scheduling for embedded systems , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).
[5] Fadi J. Kurdahi,et al. Configuration management in multi-context reconfigurable systems for simultaneous performance and power optimizations , 2000, ISSS '00.
[6] Rudy Lauwereins,et al. Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs , 2002, FPL.
[7] Javier Resano,et al. Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware , 2004, Proceedings. 41st Design Automation Conference, 2004..
[8] Zhiyuan Li,et al. Configuration management techniques for reconfigurable computing , 2002 .
[9] Li Shang,et al. Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.