The Research on Leakage Power Controlling Policies for On-Chip L2 Cache

As feature size shrinks and the frequency increases,on-chip L2 cache with large capability is the main source of leakage power in micro-processors.Supporting not only the State-Preserving but also the State-Destroying low leakage power mode,two leakage power controlling policies for L2 cache are proposed.One is the Conserved State-Preserving and State-Destroying(C-SPSD) policy;the other is the Speculative State-Preserving and State-Destroying(S-SPSD) policy.Only one copy of a data block in cache hierarchies is in the active mode,the others are turned into the low power mode.The State-Destroying mode with least leakage power should be turned into at most as possible if no obvious performance cost occurs.Compared with the traditional leakage power controlling policies for L2 cache,C-SPSD policy can save the leakage power of L2 cache more efficiently without obvious performance cost;S-SPSD policy can save the most leakage power of L2 cache and reach the best energy efficiency of whole processor.