Power-Aware FPGA Design
暂无分享,去创建一个
[1] Odysseas Koufopavlou,et al. Multi-operation cryptographic engine: VLSI design and implementation , 2005 .
[2] Sujit Dey,et al. Glitch analysis and reduction in register transfer level power optimization , 1996, DAC '96.
[3] Juho Kim,et al. Efficient algorithm for glitch power reduction , 1999 .
[4] Naehyuck Chang,et al. Flip-flop insertion with shifted-phase clocks for FPGA power reduction , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..