Network-on-Chip for Turbo Decoders

The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the addressing patterns for turbo codes in long term evolution (LTE) and High Speed Downlink Packet Access (HSDPA) are analyzed. Based on this analysis, two techniques, subnetworking and calculation sequence, are proposed for reducing the complexity of the NoC. The implementation results show that the proposed structure gives an improvement of 53% for HSDPA and 133% for LTE in throughput/area efficiency compared with state-of-the-art NoC solutions.

[1]  Amer Baghdadi,et al.  From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Norbert Wehn,et al.  A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Guido Masera,et al.  Improving Network-on-Chip-based Turbo Decoder Architectures , 2011, J. Signal Process. Syst..

[4]  Qiuting Huang,et al.  Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE , 2011, IEEE Journal of Solid-State Circuits.

[5]  Amer Baghdadi,et al.  On chip interconnects for multiprocessor turbo decoding architectures , 2011, Microprocess. Microsystems.

[6]  Guido Masera,et al.  Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  V. Derudder,et al.  A 10.37 mm2 675 mW reconfigurable LDPC and Turbo encoder and decoder for 802.11n, 802.16e and 3GPP-LTE , 2010, 2010 Symposium on VLSI Circuits.

[8]  Paul H. Siegel,et al.  VLSI architectures for metric normalization in the Viterbi algorithm , 1990, IEEE International Conference on Communications, Including Supercomm Technical Sessions.