Parallel architectures for 3-step hierarchical search block-matching algorithm

The paper describes fully pipelined parallel architectures for the 3-step hierarchical search block-matching algorithm, a fast motion estimation algorithm for video coding. The advantage of this algorithm was completely utilized by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed 3-PE, 9-PE, and 27-PE architectures provide efficient solutions for real-time motion estimations required by video applications of various data rates, from low bit-rate video to HDTV systems. >

[1]  M. GHANBARI,et al.  The cross-search algorithm for motion estimation [image coding] , 1990, IEEE Trans. Commun..

[2]  Peter Pirsch,et al.  A hierarchical multiprocessor architecture for video coding applications , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[3]  Peter Pirsch,et al.  Array architectures for block matching algorithms , 1989 .

[4]  Anil K. Jain,et al.  Displacement Measurement and Its Application in Interframe Image Coding , 1981, IEEE Trans. Commun..

[5]  R. Srinivasan,et al.  Predictive Coding Based on Efficient Motion Estimation , 1985, IEEE Trans. Commun..

[6]  Peter A. Ruetz,et al.  A high-performance full-motion video compression chip set , 1992, IEEE Trans. Circuits Syst. Video Technol..

[7]  Ming-Ting Sun,et al.  An all-ASIC implementation of a low bit-rate video codec , 1992, IEEE Trans. Circuits Syst. Video Technol..

[8]  T Koga,et al.  MOTION COMPENSATED INTER-FRAME CODING FOR VIDEO CONFERENCING , 1981 .

[9]  Ming-Ting Sun,et al.  A family of vlsi designs for the motion compensation block-matching algorithm , 1989 .

[10]  Peter Pirsch,et al.  Multiprocessor performance for real-time processing of video coding applications , 1992, IEEE Trans. Circuits Syst. Video Technol..

[11]  W. Y. Zou.  Digital HDTV compression techniques , 1991 .

[12]  Hironori Yamauchi,et al.  Architecture and implementation of a highly parallel single-chip video DSP , 1992, IEEE Trans. Circuits Syst. Video Technol..

[13]  P. R. Burfield,et al.  A VLSI implementation study of a 10 Mbit/s video decoder , 1993, Signal Process. Image Commun..

[14]  Michael Stegherr,et al.  Parameterizable VLSI architectures for the full-search block-matching algorithm , 1989 .