VLSI Architectures of Lifting-Based Discrete Wavelet Transform

The advantages of the wavelet transform over conventional transforms, such as the Fourier transform, are now well recognized. Because of its excellent locality in time-frequency domain, wavelet transform is remarkable and extensively used for signal analysis, compressing and denoising. Defining DWT by Mallat [1] provided possibility of its digitally hardware or software implementation. The discrete wavelet transform (DWT) performs a multiresolution signal analysis which has adjustable locality in both the space (time) and frequency domains [1]. Unlike the Fourier transform, the wavelet transform has many possible sets of basis functions. A trade-off can be made between the choice of basis functions and the complexity of the corresponding hardware implementations. Using finite impulse response (FIR) filters and then subsampling is the classical method for implementing the DWT. Due to the large amount of computations required, there have been many research efforts to develop new rapid algorithms [2]. In 1996, Sweldens presented a lifting scheme for a fast DWT, which can be easily implemented by hardware due to significantly reduced computations [3]. This method is entirely based on a spatial interpretation of the wavelet transform. Moreover, it provides the capability of producing new mother wavelets for the wavelet transform, based on space domain features. Due to recent advances in the technology, implementation of the DWT on field programmable gate array (FPGA) and digital signal processing (DSP) chips has been widely developed. As described in Sect. 3, in the lifting scheme the structural processing elements, including multipliers, are arranged serially; hence, the number of multipliers in each pipeline stage determines the clock speed of the structure. Based on [4], the main challenges in the hardware architectures for 1-D DWT are the processing speed and the number of multipliers, while for 2-D DWT it is the memory issue that dominates the hardware cost and the architectural complexity. The reason is the limitation of the on-chip memory and the power consumption [4,5].

[1]  Liang-Gee Chen,et al.  Memory analysis and architecture for two-dimensional discrete wavelet transform , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[2]  Joan Carletta,et al.  A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Chen-Yi Lee,et al.  A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[4]  A. Jensen,et al.  Ripples in Mathematics - The Discrete Wavelet Transform , 2001 .

[5]  Julien Reichel.  On the arithmetic and bandwidth complexity of the lifting scheme , 2001, Proceedings 2001 International Conference on Image Processing (Cat. No.01CH37205).

[6]  M. Hasan,et al.  Energy efficient novel architectures for the lifting-based discrete wavelet transform , 2007 .

[7]  Chengyi Xiong,et al.  A note on "Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet Transform" , 2006, IEEE Transactions on Signal Processing.

[8]  Bruce F. Cockburn,et al.  Efficient architectures for 1-D and 2-D lifting-based wavelet transforms , 2004, IEEE Transactions on Signal Processing.

[9]  Liang-Gee Chen,et al.  Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank , 2003, Proceedings 2003 International Conference on Image Processing (Cat. No.03CH37429).

[10]  Liang-Gee Chen,et al.  Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method , 2002, Asia-Pacific Conference on Circuits and Systems.

[11]  Liang-Gee Chen,et al.  Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[12]  Constantinos E. Goutis,et al.  Evaluation of design alternatives for the 2-D-discrete wavelet transform , 2001, IEEE Trans. Circuits Syst. Video Technol..

[13]  I. Daubechies,et al.  Wavelet Transforms That Map Integers to Integers , 1998 .

[14]  I. Daubechies,et al.  Factoring wavelet transforms into lifting steps , 1998 .

[15]  Stéphane Mallat,et al.  A Theory for Multiresolution Signal Decomposition: The Wavelet Representation , 1989, IEEE Trans. Pattern Anal. Mach. Intell..

[16]  Jhing-Fa Wang,et al.  A Block-Based Architecture for Lifting Scheme Discrete Wavelet Transform , 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[17]  Liang-Gee Chen,et al.  Lifting based discrete wavelet transform architecture for JPEG2000 , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[18]  Gianluca Piccinini,et al.  Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations , 2003, J. VLSI Signal Process..

[19]  Chengyi Xiong,et al.  Efficient Architectures for Two-Dimensional Discrete Wavelet Transform Using Lifting Scheme , 2007, IEEE Transactions on Image Processing.

[20]  In-Cheol Park,et al.  Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[21]  Awais M. Kamboh,et al.  A Scalable Wavelet Transform VLSI Architecture for Real-Time Signal Processing in High-Density Intra-Cortical Implants , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  Saeed Sadri,et al.  Investigation of Lifting-Based Hardware Architectures for Discrete Wavelet Transform , 2009, Circuits Syst. Signal Process..

[23]  Nanning Zheng,et al.  Low-power and high-speed VLSI architecture for lifting-based forward and inverse wavelet transform , 2005, IEEE Transactions on Consumer Electronics.

[24]  Liang-Gee Chen,et al.  Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform , 2005, IEEE Trans. Signal Process..

[25]  Liang-Gee Chen,et al.  Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform , 2004, IEEE Transactions on Signal Processing.

[26]  M. Suresh Babu,et al.  Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Packet Transform , 2010 .

[27]  Omid Fatemi,et al.  Pipeline, memory-efficient and programmable architecture for 2D discrete wavelet transform using lifting scheme , 2005 .

[28]  Chaitali Chakrabarti,et al.  A Survey on Lifting-based Discrete Wavelet Transform Architectures , 2006, J. VLSI Signal Process..

[29]  Chaitali Chakrabarti,et al.  A VLSI architecture for lifting-based forward and inverse wavelet transform , 2002, IEEE Trans. Signal Process..

[30]  Jer-Min Jou,et al.  Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).