Fast algorithms for IR voltage drop analysis exploiting locality

Closed form expressions and related algorithms for fast power grid analysis are proposed in this paper. The IR voltage drop at an arbitrary point in a power distribution network is determined. Two algorithms are described for non-uniform voltage supplies and non-uniform current loads distributed throughout a power grid. The principle of spatial locality is exploited to accelerate the proposed power grid analysis method. Analysis of the non-uniform power grids utilizes the principle of spatial locality. Since no iterations are required for the proposed IR drop analysis, the proposed algorithms are over 70 times faster for smaller power grids composed of less than five million nodes and over 180 times faster for larger power grids composed of more than 25 million nodes as compared to existing methods. The proposed method exhibits less than 0.5% error.

[1]  Eby G. Friedman,et al.  An area efficient fully monolithic hybrid voltage regulator , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[2]  Martin D. F. Wong,et al.  Fast algorithms for IR drop analysis in large power grid , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[3]  K. Shakeri,et al.  Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI) , 2005, IEEE Transactions on Electron Devices.

[4]  Sani R. Nassif,et al.  Multigrid-like technique for power grid analysis , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[5]  Peng Li,et al.  Locality-Driven Parallel Power Grid Optimization , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Renatas Jakushokas,et al.  Noise Issues in On-Chip Power Distribution Networks , 2011 .

[7]  Sanjay Pant,et al.  Power Grid Physics and Implications for CAD , 2007, IEEE Design & Test of Computers.

[8]  Puneet Gupta,et al.  Efficient design and analysis of robust power distribution meshes , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[9]  Yici Cai,et al.  Partitioning-based approach to fast on-chip decap budgeting and minimization , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[10]  Yehea I. Ismail,et al.  DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  F. Y. Wu.  Theory of resistor networks: the two-point resistance , 2004 .

[12]  Kaushik Roy,et al.  Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Sachin S. Sapatnekar,et al.  Hierarchical random-walk algorithms for power grid analysis , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[14]  Eby G. Friedman,et al.  Fast algorithms for power grid analysis based on effective resistance , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[15]  Eby G. Friedman,et al.  Power Distribution Networks with On-Chip Decoupling Capacitors , 2007 .

[16]  Eli Chiprout.  Fast flip-chip power grid analysis via locality and grid shells , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[17]  G. Venezian,et al.  On the resistance between two points on a grid , 1994 .

[18]  Yici Cai,et al.  Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Sani R. Nassif,et al.  Random walks in a supply network , 2003, DAC '03.

[20]  Eby G. Friedman,et al.  Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors , 2010, 23rd IEEE International SOC Conference.

[21]  Sani R. Nassif,et al.  Power grid analysis using random walks , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.