Access time analysis of dynamic MOS RAM

Among the high-performance factors of dynamic MOS RAM's, high speed is the most important and its research and development has been carried out actively. However, a model for access time analysis which serves as a guide for the realization of high-speed access time has not been proposed extensively nor is its quantitative analysis sufficient. It is shown in this paper from the factor analysis of 64K dynamic MOS RAM access time that approximately 50% of the access time is spent on the sense time to read a small signal. Further, an analytical relation for the delay time of basic clock circuits is derived. Also, a model for the access time analysis is proposed which represents the access time as a sum of word line delay, bit line delay, sense time, and signal delay in the peripheral circuits. It is shown that the calculated value and the measured value of the access time of the fabricated 64K dynamic RAM agree to within 15% error. This confirms the effectiveness of the model. Further, from the access time sensitivity analysis using the access time analysis model, the simplicity of the peripheral circuits, the increase of the conductance value, and the reduction of the threshold voltage are shown to be effective for high speed.