An ultra low die area 8-b ADC and its generic calibration logic

The 8-bit voltage mode subrange A/D converter described in this paper operates in a mid-input signal frequency range of up to 20 MHz and requires at least an order of magnitude lower die area (0.06 mm2) than other A/D converters with a similar resolution. Moreover, it dissipates only 4.5 mW power and is supported by a calibration logic that is general enough to be used by several other measurement and instrumentation applications that require a real time adjustment of the amplitude and the level of their differential signals. This voltage mode subrange A/D converter architecture is actually an asynchronous two-step A/D converter that is based on a novel integer division operation. The current mode implementation of such an integer divider has already been employed by the authors in an innovative low area/power binary tree A/D conversion architecture. The voltage mode implementation of the integer divider allows the realization of the higher speed and lower power/area subrange A/D converter that is presented in this article.

[1]  Sergio Saponara.  Configurable array of low-complex SAR ADCs , 2011 .

[2]  Li-Rong Zheng,et al.  An 8-bit 166nw 11.25 kS/s 0.18um two-Step-SAR ADC for RFID applications using novel DAC architecture , 2010, NORCHIP 2010.

[3]  Suat U. Ay.  A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS , 2011 .

[4]  Nikos Petrellis,et al.  An ultra low area asynchronous combo 4/8/12-bit/quaternary A/D converter based on integer division , 2010, Microelectron. J..

[5]  C.A.T. Salama,et al.  An 8-bit 12.5-GSample/s SiGe ADC , 2010 .

[6]  Jan Craninckx,et al.  A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  Niket Agrawal,et al.  A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS , 2010 .

[9]  Jianhui Wu,et al.  A 1.8-V 3.1 mW successive approximation ADC in system-on-chip , 2008 .

[10]  Pasquale Daponte,et al.  A state of the art on ADC error compensation methods , 2004, Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.04CH37510).

[11]  Kyu-Young Kim,et al.  8 mW 1.65-Gbps continuous-time equalizer with clock attenuation detection for digital display interface , 2010 .

[12]  Franco Maloberti,et al.  An ultra-low power successive approximation A/D converter with time–domain comparator , 2010 .

[13]  Gabor C. Temes,et al.  A 14-bit dual-path 2-0 MASH ADC with dual digital error correction , 2009 .

[14]  Seung-Hoon Lee,et al.  A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments , 2010 .

[15]  Augusto Gutierrez-Aitken,et al.  An Ultra-Wideband 7-Bit 5 Gsps ADC Implemented in Submicron InP HBT Technology , 2007, 2007 IEEE Compound Semiconductor Integrated Circuits Symposium.

[16]  Fan Ye,et al.  A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC , 2010 .

[17]  Junyan Ren,et al.  An 80-MS/s 14-bit pipelined ADC featuring 83 dB SFDR , 2010 .

[18]  Andrea Baschirotto,et al.  A 90-nm CMOS, 8-bit pipeline ADC with 60-MHz bandwidth and 125-MS/s or 250-MS/s sampling frequency , 2010 .

[19]  M. Furuta,et al.  A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques , 2007, IEEE Journal of Solid-State Circuits.

[20]  Fan Ye,et al.  A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS , 2009 .

[21]  Yusuf Leblebici,et al.  Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).