A Bond Graph Approach for Constraint based Verification of Analog Circuits

The computer-aided design community is in need of novel methodologies for the verification of analog circuits because of the growing importance of such circuits in embedded system designs. This paper demonstrates a verification flow of analog circuit functional properties. In the proposed approach, system equations are automatically extracted from an analog circuit description by means of bond graph transformations. Property verification based on abstract model checking and constraint solving are then applied to the extracted equations. The benefit of using bond graphs as a modelling framework is their representation of circuits using the concepts of energy flow, effort and conservation. Hence, allowing for several levels of abstraction. Our methodology has the advantage of avoiding exhaustive simulation normally encountered in the verification of analog circuits. To this end, we have used a set of tools (i.e., Dymola, HSolver, HybridSal and Mathematica) to implement the verification flow. We illustrate the methodology on several analog examples including Colpitts and tunnel diode oscillators.

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