An ultra-high-speed direct digital synthesizer with nonlinear DAC and wave correction ROM

This paper presents a novel direct digital synthesizer (DDS) architecture combining Nonlinear DAC with a small-sized wave-correction-ROM (WCR), which achieves both high operating speed and accuracy. A 6 GHz 8-bit DDS chip based on the proposed architecture is designed and fabricated in a 60 GHz GaAs HBT technology. The major blocks of the DDS MMIC based on ECL logic includes an 8-bit pipelined accumulator, an 8 × 8 × 3-bit WCR, two combined digital-to-analog converters (DACs) and an analog Gilbert Cell for sine-wave generation, a 3-to-7 thermometer coder, digital logic gates and registers. A method of using a series of RC networks to terminate the clock tree together with a pot-layout simulation scheme is developed to maintain the clock tree signal integrity. The DDS chip is tested using an on-wafer measurement approach. The measured spurious free dynamic range (SFDR) is 33.96 dBc with a 2.367 GHz output using a 6 GHz maximum clock frequency. The measurement also shows an average SFDR of 37.5 dBc and the worst case SFDR of 31.4 dBc (FCW = 112) within the entire Nyquist band under a 5 GHz clock. The chip occupies 2.4 × 2 mm2 of area and consumes a 3.27 W of power from a single −4.6 V power supply.