论文信息 - An architecture for integrated reliability simulators using analog hardware description languages

An architecture for integrated reliability simulators using analog hardware description languages

A new architecture for integrated reliability simulators is presented. The architecture is compatible with analog hardware description language simulation environments. Simulator integration is achieved by incorporating the reliability evaluation routines into the component templates through the use of analog states. An internal simulation control mechanism is substituted for the external control shell found in conventional reliability simulators. The architecture supports iterative and multi-step reliability simulation schemes. A prototype reliability simulator for amorphous silicon circuits is also presented.

Savvas G. Chamberlain | S. M. GadelRab | James A. Barby

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