Characterization of opens in logic circuits

We present an algorithm for extracting opens in rectilinear circuit layouts using a plane-sweep technique. An implementation of the algorithm is used to characterize realistic opens in combinational circuit layouts. The occurrence of three types of opens possible in standard cells is examined. The number of single and multiple stuck-at faults due to opens in benchmark circuits is determined, assuming that floating nodes cause stuck-at faults. The distribution of open critical area between cells and routing, and between circuit layers is measured for the benchmark circuits.<<ETX>>

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