An all-digital phase-locked loop with fast acquisition and low jitter

An all-digital phase-locked loop that achieves fast acquisition and low jitter was developed for high-speed clock generation. By employing a time-to-digital converter (TDC), the frequency difference is precisely measured and converted to the control word of the digital oscillator. Using this feature, the ADPLL has a faster lock-in time than previous digital phaselocked loops. The ADPLL was implemented using a 0.9 V 32 nm practical transistor model (PTM). The simulation results show that the proposed ADPLL achieves 5 and 10 reference cycles of frequency and phase acquisitions at 700 MHz with peak to peak jitter < 53 ps.

[1]  P. Larsson.  A 2-1600 MHz 1.2-2.5 V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[2]  Soo-Won Kim,et al.  A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition , 2001 .

[3]  P. Nilsson,et al.  A digitally controlled PLL for SoC applications , 2004, IEEE Journal of Solid-State Circuits.

[4]  H. Sarbazi-Azad,et al.  Performance evaluation of Butterfly on-Chip Network for MPSoCs , 2008, 2008 International SoC Design Conference.

[5]  Meng-Chang Lee,et al.  All-digital PLL and GSM/EDGE transmitter in 90nm CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[6]  Soo-Won Kim,et al.  A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application , 2000 .

[7]  D. Boerstler.  A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz , 1999, IEEE J. Solid State Circuits.

[8]  V. von Kaenel.  A high-speed, low-power clock generator for a microprocessor application , 1998 .

[9]  J. Lundberg,et al.  An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors(Special Issue on the 1994 VLSI Circuits Symposium) , 1995 .

[10]  H. Sarbazi-Azad,et al.  The Kautz mesh: A new topology for SoCs , 2008, 2008 International SoC Design Conference.