Apparatus and method for controlling a cache

The present invention relates to a cache control apparatus and method that can reduce the miss penalty. The cache control apparatus according to the present invention is the to be accessed by the processor if the first level cache, a first level of the cache associated with, with respect to the data request command, the first level cache for storing the data of the memory fails the data call the second level cache, and a second pre-fetch buffer, and the first is connected to the level cache, the first level cache to the first and the store 2 is connected to the level caches and temporary data to be transferred to the core from the first and second level cache, and a write buffer for receiving address information and data. In addition, the cache control method according to the invention if the the step of calling the data in accordance with a data request command with respect to the phase, a first level cache for receiving a data request command, a first level cache miss for the data call, a step to read the successive lines of the lines including a data request command, when a cache read operation during the first level cache, or comprising the steps of: temporarily storing data to be transmitted to the core from the second level cache, the pre-fetch buffer and a cache write operation the and a step of receiving the address information, the data of the first level cache.