A Four-step Iterative Design Optimization Technique for DLHL IMPATTs

ABSTRACT A proposed four-step iterative optimization technique has been used to design a double low-high-low (DLHL) impact avalanche transit time (IMPATT) diode based on Si for 60 GHz operation. Initially the position of the charge bumps in both n- and p-epitaxial layers followed by the widths of those and the ratio of high to low doping concentrations have been varied to obtain the maximum large-signal DC to radio frequency (RF) conversion efficiency from the device. Finally the bias current density is varied within a specified range to obtain the optimum value of it for which the DC to RF conversion efficiency of the device is maximum. The above-mentioned four optimization steps have been repeated until the method converges to provide a stable optimized DC to RF conversion efficiency. A large-signal simulation technique based on non-sinusoidal voltage excitation model developed by the authors is used for this purpose. The large-signal properties of the optimized DLHL Si IMPATT have been simulated and those are compared with the experimental results reported earlier. The said comparison shows that the optimized DLHL diode is capable of delivering significantly higher RF power output with greater DC to RF conversion efficiency at 60 GHz as compared to its un-optimized counterpart.

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