EISC 임베디드 코어의 Pipeline 성능 향상을 위한 Selective Pipeline Flush 구현

This paper proposes a hardware structure that can improve performance at the deep pipelined Extendable Instruction Set Computer (EISC) processor with a branch predictor. When the branch misprediction occurs, the processor flushes all the pipeline stages, thus wastes a lot of clock cycles. The deeper pipelined processor incurs higher branch misprediction penalty. By introducing our Selective Pipeline Flush(SPF) Logic, we could reduce the branch misprediction penalty and improve the total performance of the EISC embedded processor core.