Power estimation techniques for Reed-Muller logic circuits

A power estimation approach was proposed for Reed-Muller (RM) logic circuits. Given the signal probability and transition density of input signals, AND/XOR gates were decomposed into a number of 2-input gate tree, its switching activity was calculated to estimate the power dissipation. Experimental results indicated that the proposed approach can well predict the power dissipation for RM logic circuits without detail process information.