An 81 MHz, 1280 /spl times/ 720pixels /spl times/ 30frames/s MPEG-4 video/audio CODEC processor

A high-definition MPEG-4 CODEC processor capable of encoding 720p images (1280/spl times/720 pixels 30f/s) at 81MHz is presented. The CODEC is implemented with only 390k gates and an 80 kB SRAM. It is fabricated in a 0.13/spl mu/m CMOS process on a 5.6mm/spl times/5.6mm die.

[1]  Y. Watanabe,et al.  An MPEG-4 video LSI with an error-resilient codec core based on a fast motion estimation algorithm , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[2]  Ken-ichi Ishida,et al.  22.1 A 27MHz 11.1mW MPEG-4 Video Decoder LSI for Mobile Application , 2002 .

[3]  R. Satomura,et al.  A 133 MHz 170 mW 10 /spl mu/A standby application processor for 3G cellular phones , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[4]  K. Ohmori,et al.  A 160 mW, 80 nA standby, MPEG-4 audiovisual LSI with 16 Mb embedded DRAM and a 5 GOPS adaptive post filter , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[5]  山本 英明,et al.  A 160mW, 80nA Standby, MPEG-4 Audiovisual LSI with 16Mb Embedded DRAM and a 5GOPS Adaptive Post Filter(VSLI一般(ISSCC'03関連特集)) , 2003 .

[6]  Kentaro Ogura,et al.  A 133MHz 170mW 10μA standby application processor for 3G cellular phones , 2002 .