Design optimization and space minimization considering timing and code size via retiming and unfolding

Abstract The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such as software pipelining and loop unfolding, and their effects on multiple design parameters. This paper presents an Integrated Framework for Design Optimization and Space Minimization (IDOM) toward finding the minimum configuration satisfying timing and code size constraints. We show an effective way to reduce the design space to be explored through the study of the fundamental properties and relationships among retiming function, unfolding factor, timing, and code size. We present theorems to show that a small set of feasible unfolding factors can be obtained effectively to produce high-quality designs. The IDOM algorithm is proposed to generate a minimal configuration of the design by integrating software pipelining, unfolding, and code size reduction techniques. The experimental results on a set of DSP benchmarks show the efficiency and effectiveness of our technique.

[1]  Edwin Hsing-Mean Sha,et al.  Scheduling Data-Flow Graphs via Retiming and Unfolding , 1997, IEEE Trans. Parallel Distributed Syst..

[2]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[3]  B. Ramakrishna Rau,et al.  Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing , 1981, MICRO 14.

[4]  Edwin Hsing-Mean Sha,et al.  Efficient design exploration based on module utility selection , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Markku Renfors,et al.  The maximum sampling rate of digital filters under hardware speed constraints , 1981 .

[6]  Edwin Hsing-Mean Sha,et al.  Rotation Scheduling: A Loop Pipelining Algorithm , 1993, 30th ACM/IEEE Design Automation Conference.

[7]  Edwin Hsing-Mean Sha,et al.  Extended retiming: optimal scheduling via a graph-theoretical approach , 1999, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).

[8]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[9]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[10]  Francesco Curatelli,et al.  Software synthesis for real-time information processing systems , 1995, Code Generation for Embedded Processors.

[11]  B. Ramakrishna Rau,et al.  Instruction-level parallel processing: History, overview, and perspective , 2005, The Journal of Supercomputing.

[12]  Robert A. Walker,et al.  A solution methodology for exact design space exploration in a three-dimensional design space , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Guang R. Gao,et al.  Scheduling and mapping: software pipelining in the presence of structural hazards , 1995, PLDI '95.

[14]  David A. Padua,et al.  Dependence graphs and compiler optimizations , 1981, POPL '81.

[15]  Xiaobo Sharon Hu,et al.  Predicting timing behavior in architectural design exploration of real-time embedded systems , 1997, DAC.

[16]  Edwin Hsing-Mean Sha,et al.  Static scheduling for synthesis of DSP algorithms on various models , 1995, J. VLSI Signal Process..

[17]  Alain Darte,et al.  Loop Shifting for Loop Compaction , 2004, International Journal of Parallel Programming.

[18]  Charles E. Leiserson,et al.  Retiming synchronous circuitry , 1988, Algorithmica.

[19]  Hugo De Man,et al.  Software synthesis for real-time information processing systems , 1995 .

[20]  Qingfeng Zhuge,et al.  Optimal code size reduction for software-pipelined and unfolded loops , 2002, 15th International Symposium on System Synthesis, 2002..

[21]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[22]  Edwin Hsing-Mean Sha,et al.  Code size reduction technique and implementation for software-pipelined DSP applications , 2003, TECS.

[23]  B. Ramakrishna Rau,et al.  Iterative modulo scheduling: an algorithm for software pipelining loops , 1994, MICRO 27.

[24]  B. R. Rau,et al.  Code generation schema for modulo scheduled loops , 1992, MICRO 1992.

[25]  Krishna V. Palem,et al.  Design space optimization of embedded memory systems via data remapping , 2002, LCTES/SCOPES '02.

[26]  Richard A. Huff,et al.  Lifetime-sensitive modulo scheduling , 1993, PLDI '93.

[27]  Edwin Hsing-Mean Sha,et al.  Optimal code size reduction for software-pipelined loops on DSP applications , 2002, Proceedings International Conference on Parallel Processing.