A 64/256 QAM receiver chip for high-speed communications

This paper presents the implementation of a 64/256 QAM receiver chip for high-speed multimedia data communication that supports DOCSIS (Data Over Cable Service Interface Specification) of MCNs (Multimedia Cable Network System). The implemented architecture consists of the upstream unit and the downstream unit that includes the demodulator symbol timing recovery, carrier recovery and a DFE equalizer. The equalizer uses MMA (Multi-Modulus Algorithm). The 64/256 QAM receiver can support high-speed data rate up to 64 Mbps and can also provide the symbol rate up to 8 Mband which is faster than that of existing QAM receivers. We have used the 0.35 /spl mu/m standard cell library. The total number of gates is about 210000 and the implemented 64/256 QAM receiver chip is currently being fabricated with delivery expected soon.

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