Design of A Novel Asynchronous Reconfigurable Architecture for Cryptographic Applications

Cryptographic algorithms are usually compute-intensive and more efficiently implemented in hardware than in software running on general-purpose processors. However, systems which use hardware implementations have significant drawbacks: they are unable to respond to flaws discovered in the implemented algorithm or to changes in standards. By taking advantage of FPGA technology, some work offers high performance and flexible solutions for cryptographic algorithms. But FPGAs still have some drawbacks. To overcome these shortages of FPGA, such as redundant routing resources which increase chip area and power consumption, a novel asynchronous reconfigurable cryptographic engine (ARCEN) is introduced. In this architecture, reconfigurable cryptographic array is the kernel. It routes signals asynchronously between adjacent cells through neighbor-to-neighbor wires with 4-phase handshaking protocol. Computation circuit for reconfigurable cell is developed with modified DSDCVS logic. On the implementation of cryptographic algorithms such as AES, the architecture shows a better performance than FPGA

[1]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[2]  William H. Mangione-Smith,et al.  A case study of partially evaluated hardware circuits: Key-specific DES , 1997, FPL.

[3]  Viktor K. Prasanna,et al.  An adaptive cryptographic engine for internet protocol security architectures , 2004, TODE.

[4]  Scott Hauck,et al.  The Chimaera reconfigurable functional unit , 1997, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Ramalingam Sridhar,et al.  Data-driven self-timed differential cascode voltage switch logic , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[6]  Kai Wing Tse,et al.  Implementation of the data encryption standard algorithm with FPGAs , 1994 .

[7]  Seth Copen Goldstein,et al.  A High-Performance Flexible Architecture for Cryptography , 1999, CHES.

[8]  Reiner W. Hartenstein,et al.  Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures , 2000, PATMOS.

[9]  Ramalingam Sridhar,et al.  A data-driven micropipeline structure using DSDCVSL , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[10]  Oliver Chiu-sing Choy,et al.  A New Control Circuit for Asynchronous Micropipelines , 2001, IEEE Trans. Computers.

[11]  Mark Shand,et al.  Fast implementations of RSA cryptography , 1993, Proceedings of IEEE 11th Symposium on Computer Arithmetic.

[12]  Odysseas G. Koufopavlou,et al.  Implementation of the SHA-2 Hash Family Standard Using FPGAs , 2005, The Journal of Supercomputing.

[13]  Wayne Luk,et al.  Reconfigurable elliptic curve cryptosystems on a chip , 2005, Design, Automation and Test in Europe.

[14]  Luis A. Plana,et al.  An investigation into the security of self-timed circuits , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..