Compensation and Calibration Techniques for Current-Steering DACs

Digital-to-analog converters (DACs) are pervasive, critical components for radios and various signal processing systems. Therefore, a myriad of research efforts, covering architectural, circuit, and technological aspects have been made towards improving the performance of DACs. However, the quest to achieve stringent dynamic linearity requirements (>70 dBc SFDR ) over many gigahertz of bandwidth presents grand challenges to designers and high-yield manufacturers. In light of these challenges, various calibration and compensation techniques have evolved over the past two decades to overcome design and process technology variations and limitations.

[1]  Yintang Yang,et al.  A High-SFDR 14-bit 500 MS/s Current-Steering D/A Converter in $0.18~\mu $ m CMOS , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Arthur H. M. van Roermund,et al.  Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[3]  Miaochen Wu,et al.  22.7 A 14b 4.6GS/s RF DAC in 0.18μm CMOS for cable head-end systems , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[4]  Yonghua Cong,et al.  A 1.5 V 14 b 100 MS/s self-calibrated DAC , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[5]  Ian Galton,et al.  Why Dynamic-Element-Matching DACs Work , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Gabriele Manganaro Advanced Data Converters: Index , 2011 .

[7]  R. Adams,et al.  A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[8]  Arthur H. M. van Roermund,et al.  D/A conversion: amplitude and time error mapping optimization , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

[9]  J. Jacob Wikner,et al.  Modeling of CMOS digital-to-analog converters for telecommunication , 1999 .

[10]  Arthur H. M. van Roermund,et al.  Timing error measurement for highly linear wideband Digital to Analog Converters , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[11]  Gil Engel,et al.  A 14b 3/6GHz current-steering RF DAC in 0.18μm CMOS with 66dB ACLR at 2.9GHz , 2012, 2012 IEEE International Solid-State Circuits Conference.

[12]  Michel Steyaert,et al.  A 12-bit intrinsic accuracy high-speed CMOS DAC , 1998, IEEE J. Solid State Circuits.

[13]  A. Maeda,et al.  A 10-bit 70 MS/s CMOS D/A converter , 1991, Digest of Technical Papers., 1990 Symposium on VLSI Circuits.

[14]  K. Bult,et al.  A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2 , 1998, IEEE J. Solid State Circuits.

[15]  Piero Malcovati,et al.  Analysis of the ideal SFDR limit for an N bit digital-to-analog converter , 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

[16]  Kok Lim Chan,et al.  Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs , 2008, IEEE Journal of Solid-State Circuits.

[17]  Degang Chen,et al.  New calibration technique for current-steering DACs , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[18]  P. Vorenkamp,et al.  Fully bipolar, 120-Msample/s 10-b track-and-hold circuit , 1992 .

[19]  Arthur H. M. van Roermund,et al.  A novel timing-error based approach for high speed highly linear Mixing-DAC architectures , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[20]  Yung-Cheng Chu,et al.  A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[21]  N. Yokozawa,et al.  An untrimmed D/A converter with 14-bit resolution , 1981, IEEE Journal of Solid-State Circuits.

[22]  W. Groeneveld,et al.  A self calibration technique for monolithic high-resolution D/A converters , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[23]  M. Sumathi Performance and analysis of CML Logic gates and latches , 2007, 2007 International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications.

[24]  Willy Sansen,et al.  Analog circuit design : high-speed analog-to-digital converters; mixed-signal design; PLL's and synthesizers , 2000 .

[25]  Tai-Haur Kuo,et al.  A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique , 2014, IEEE Journal of Solid-State Circuits.

[26]  Yvon Savaria,et al.  Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[27]  Waleed Khalil,et al.  Architectural trends in GHz speed DACs , 2012, NORCHIP 2012.

[28]  R. Baird,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .

[29]  Kwang-Hyun Baek,et al.  A 1.6GS/s 12b return-to-zero GaAs RF DAC for multiple Nyquist operation , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[30]  Bang-Sup Song,et al.  A self-trimming 14b 100MSample/s CMOS DAC , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[31]  Arthur H. M. van Roermund,et al.  A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[32]  Tao Chen,et al.  The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[33]  Arthur H. M. van Roermund,et al.  Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[34]  Munkyo Seo,et al.  DC - 10GHz RF Digital to Analog Converter , 2011, 2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

[35]  Robert H. M. van Veldhoven,et al.  A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping , 2011, IEEE Journal of Solid-State Circuits.

[36]  D. Leenaerts,et al.  A 12b 500MS/s DAC with >70dB SFDR up to 120MHz in 0.18μm CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[37]  I. Galton,et al.  A rigorous error analysis of D/A conversion with dynamic element matching , 1995 .

[38]  Harrie Gunnink,et al.  11.7 A 240mW 16b 3.2GS/s DAC in 65nm CMOS with <-80dBc IM3 up to 600MHz , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[39]  Vipul J. Patel,et al.  InP HBT/Si CMOS-Based 13-Bit 1.33Gsps Digital-to-Analog Converter with >70 dB SFDR , 2012, 2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

[40]  Bob Jewett,et al.  A 7.2-GSa/s, 14-bit or 12-GSa/s, 12-bit DAC in a 165-GHz fT BiCMOS process , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[41]  Bang-Sup Song,et al.  A 14 b 100 Msample/s CMOS DAC designed for spectral performance , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[42]  Sungkyung Park,et al.  A digital-to-analog converter based on differential-quad switching , 2002, IEEE J. Solid State Circuits.

[43]  Mike Shuo-Wei Chen,et al.  27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[44]  Waleed Khalil,et al.  A Time-Interleaved Multimode $\Delta\Sigma$ RF-DAC for Direct Digital-to-RF Synthesis , 2016, IEEE Journal of Solid-State Circuits.

[45]  Arthur H. M. van Roermund,et al.  DDL-based calibration techniques for timing errors in current-steering DACs , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[46]  Yu Lin,et al.  A 12 bit 2.9 GS/s DAC With IM3 $ ≪ -$60 dBc Beyond 1 GHz in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[47]  H. Hegt,et al.  An on-chip self-calibration method for current mismatch in D/A converters , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[48]  M. Tiilikainen A 1.8V 20mW 1mm214b 100Msample/s CMOS DAC , 2000, Proceedings of the 26th European Solid-State Circuits Conference.

[49]  Rudy J. van de Plassche,et al.  Dynamic element matching for high-accuracy monolithic D/A converters , 1976 .

[50]  Anne-Johan Annema,et al.  An Interleaved Full Nyquist High-Speed DAC Technique , 2015, IEEE Journal of Solid-State Circuits.

[51]  B. Bakkaloglu,et al.  A Linear $\Sigma$–$\Delta$ Digital IF to RF DAC Transmitter With Embedded Mixer , 2008, IEEE Transactions on Microwave Theory and Techniques.

[52]  Liang Zhou,et al.  A multi-bit sigma-delta modulator and new DWA used in an audio DAC , 2010, 2010 2nd International Conference on Computer Technology and Development.

[53]  G. Gielen,et al.  A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration , 2007, IEEE Journal of Solid-State Circuits.

[54]  Eby G. Friedman,et al.  A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators , 2008, 2008 IEEE International SOC Conference.

[55]  Marian Verhelst,et al.  Systematic Analysis of Interleaved Digital-to-Analog Converters , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[56]  Behzad Razavi The future of radios , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[57]  W. Sansen,et al.  A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[58]  Thu-Ji Lin,et al.  A 200-MHz CMOS x/sin(x) digital filter for compensating D/A converter frequency response distortion , 1991 .

[59]  Peter Stubberud,et al.  An analysis of dynamic element matching flash digital-to-analog converters , 2001 .

[60]  Arthur H. M. van Roermund,et al.  9.6 A 5.3GHz 16b 1.75GS/S wideband RF Mixing-DAC achieving IMD<-82dBc up to 1.9GHz , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[61]  Bang-Sup Song,et al.  A 14b , 100-MS / s CMOS DAC Designed for Spectral Performance , 1999 .

[62]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[63]  Toru Sai,et al.  A 14-bit MOS DAC with current sources free from power-line voltage drop and with output circuits free from code-dependent variable time constant , 2009, 2009 European Conference on Circuit Theory and Design.

[64]  Y Yongjian Tang Smart and high-performance digital-to-analog converters with dynamic-mismatch mapping , 2010 .

[65]  Jiunn-Tsair Chen,et al.  A 14-b 150 MS/s CMOS DAC with Digital Background Calibration , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[66]  Georgi Radulov,et al.  A Self-calibrating current-steering 12-bit DAC based on new 1-bit self-test scheme , 2004 .

[67]  Georges Gielen,et al.  A 14-bit intrinsic accuracy Q2 random walk CMOS DAC , 1999, IEEE J. Solid State Circuits.

[68]  Bertrand Meyer Wide-Bandwidth High Dynamic Range D/A Converters , 1995 .

[69]  S. Boumaiza,et al.  Ultimate Transmission , 2012, IEEE Microwave Magazine.

[70]  Payam Heydari,et al.  Design of ultra high-speed CMOS CML buffers and latches , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[71]  W. Sansen,et al.  SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[72]  Swapna Banerjee,et al.  500 MHz differential latched current comparator for calibration of current steering DAC , 2014, Proceedings of the 2014 IEEE Students' Technology Symposium.

[73]  Qi Wei,et al.  A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[74]  Tao Chen,et al.  The Analysis and Improvement of a Current-Steering DAC's Dynamic SFDR—II: The Output-Dependent Delay Differences , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[75]  Waleed Khalil,et al.  A time-interleaved multi-mode ΔΣ RF-DAC for direct digital-to-RF synthesis , 2015, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).