Embedded applications today require high computational power that is not met by current FPGA-based soft processors. Although performance of data-parallel applications can be addressed by custom-designed hardware accelerators, such an approach is difficult for embedded software developers with little hardware design experience. Instead, vector processing can be used to speed up these same data-parallel applications. The vector programming model is easy to understand by software developers, making it easier for them to extract the parallelism without any hardware design knowledge. This paper proposes a soft vector processor for the Stratix III FPGA that can be scaled to different levels of performance and resource utilization. It has several configurable features that can be included or excluded to optimize the soft processor for a given application. Performance estimates of the soft vector processor using three embedded benchmark kernels show speedup of up to 16.6 x over an idealized Nios II processor while using 10.9 x the area.
[1]
Wonyong Sung,et al.
An FPGA based SIMD processor with a vector memory unit
,
2006,
2006 IEEE International Symposium on Circuits and Systems.
[2]
Christoforos E. Kozyrakis,et al.
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
,
2002,
MICRO.
[3]
Stephen Dean Brown,et al.
A Multithreaded Soft Processor for SoPC Area Reduction
,
2006,
2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.
[4]
Shuai Wang,et al.
Vector Processing Support for FPGA-Oriented High Performance Applications
,
2007,
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).
[5]
John Wawrzynek,et al.
Vector microprocessors
,
1998
.
[6]
Pradeep K. Dubey,et al.
How Multimedia Workloads Will Change Processor Design
,
1997,
Computer.