Chip-level ESD verification

In this chapter, the challenge of the last stages of the race, namely checking a complete IC with, eventually, several tens of millions of gates and many hundreds of I/O pins, is addressed. There are two basic approaches that are discussed in this chapter: formal verification and electrical simulation at chip level. This chapter discusses how an ESD fail can be extracted out of multiple combinations of possible discharge paths by a chip-level simulation. There are, in principle, two different failure mechanisms, which have to be considered when an IC is ESD stressed, the local damage of devices and the discharge path via the supply lines leads to fail. A final evaluation of the ESD protection measures on the complete IC is required to avoid errors in the integration of all the different ESD protection components. As this final check also includes core circuitry, and numerous I/O and supply cells, a straightforward circuit simulation is not applicable because of the likely numerical problems. The problem of extracting more simplified (ESD) models that can be treated within a chip-level ESD simulation without neglecting the ESD critical issues has not yet been solved. In this chapter, the requirements for such a task have been collected and a proposal for the principle of a chip-level ESD simulation flow has been made.