Fast RSSI circuit using novel power detector for wireless communication

This paper describes a fast received signal strength indicator (RSSI) circuit for wireless communication application. It is developed using a novel power detector with a fast settling time. The power detector is consisted of a variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide gain range in a closed loop form. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In 0.18 mum CMOS process, the RSSI value settles down in 20 mus with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a Personal Handy-phone System (PHS) receiver. The active area is 0.8 mm times 0.8 mm.

[1]  Wooi Gan Yeoh,et al.  A 90nm CMOS Variable-Gain Amplifier and RSSI Design for Wide-band Wireless Network Application , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[2]  Suhwan Kim,et al.  A 0.25-$\mu$m CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture , 2007, IEEE Journal of Solid-State Circuits.

[3]  Chao Yang,et al.  Precise RSSI with High Process Variation Tolerance , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[4]  Shih-Chieh Chang,et al.  Performance and wake-up schedule optimization of power gating design , 2008, 2008 International SoC Design Conference.

[5]  G. Krasser,et al.  A single chip FSK/ASK 900 MHz transceiver in a standard 0.25 um CMOS technology , 2001, 2001 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (IEEE Cat. No.01CH37173).

[6]  Hsi-Pin Ma,et al.  A low power ZigBee baseband processor , 2008, 2008 International SoC Design Conference.

[7]  Deog-Kyoon Jeong,et al.  Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver , 2003 .

[8]  F. Murden,et al.  A new paradigm for base station receivers: high IF sampling + digital filtering , 1997, 1997 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Technical Papers.

[9]  Chorng-Kuang Wang,et al.  A 15mW 280MHz 80dB gain CMOS limiting/logarithmic amplifier with active cascode gain–enhancement , 2002, Proceedings of the 28th European Solid-State Circuits Conference.