A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture

This paper presents a hybrid-type TCAM architecture which can utilize the benefits of both NOR and NAND-type TCAM cells: high speed and low power. A hidden bank selection scheme is proposed to activate limited amount of cells during the search operation avoiding additional timing penalty. Match fine repeaters and sub-match fine scheme are used for fast NAND search operation. A test chip with 144-kb TCAM capacity is implemented using 0.1-/spl mu/m 1.2-V CMOS process to verify the proposed schemes. It shows 2.2 ns of match evaluation time on a 144-bit data search with 0.7 fJ/bit/search energy efficiency.

[1]  S. R. Ramirez-Chavez.  Encoding don't cares in static and dynamic content-addressable memories , 1992 .

[2]  P. Glenn Gulak,et al.  Architectures for large-capacity CAMs , 1995, Integr..

[3]  K. J. Schultz,et al.  Fully Parallel 30-MHz , 2 . 5-Mb CAM , 1998 .

[4]  Tutomu Murase,et al.  A longest prefix match search engine for multi-gigabit IP processing , 2000, 2000 IEEE International Conference on Communications. ICC 2000. Global Convergence Through Communications. Conference Record.

[5]  Narayanan Vijaykrishnan,et al.  A novel low power CAM design , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[6]  Walid Dabbous,et al.  Survey and taxonomy of IP address lookup algorithms , 2001, IEEE Netw..

[7]  James B. Kuo,et al.  A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell , 2001 .

[8]  Yingtao Jiang,et al.  CAM-based label search engine for MPLS over ATM networks , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).

[9]  A. Sheikholeslami,et al.  A current-saving match-line sensing scheme for content-addressable memories , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..