Research on reliable on-chip network using asynchronous logic

With the development of silicon technology, the scalability and complexity of SoC greatly challenge traditional on-chip interconnection, such as on-chip buses. On-chip networks are efficient architectures to solve the problem of onchip transmission. When silicon industry enters deep submicron era, the reliability of on-chip networks are becoming a protruding problem. The paper addresses the issues using asynchronous logic to guarantee the reliability of on-chip networks. An on-chip network architecture is proposed. Based on experimental results, asynchronous logic greatly improves the reliability of on-chip transmission under the conditions of supply voltage change, wire interference,EMI,clock skew and soft error.