Modeling of single event upsets for fault-tolerant system validation

Technical advances in VLSI fabrication have pushed the device size to the submicron region, making the circuits more susceptible t o high energy particles. Therefore, the need for studying the effects of single event upsets (SEUs) due t o a-particles on system level operation in aerospace applications is greater than ever before, especially for critical systems. Since an a-particle initially produces electrical level effects, electrical level simulators need to be used for accuracy reasons. However, simulating a system a t the electrical level is prohibitively time consuming. A high level simulator would be much faster, but i t requires a high level model of the SEUs. The primary goal of this paper is to present a methodology for developing a latch-level model of SEUs to be used in a high level simulat,or. T h e methodology consists of two stages: the first stage involves modeling the behavior of the latches t o transient pulses, and the second st.age involves a gate-level timing simulator t o propagate a given a-particle hit t o the lat,ches. Using this met,hodology, latch flip distributions are obtained for a set. of benchmark circuits. The dist,ributions show the need for mult,iple-bit error injections in system level validation.