Processing N-ary trees in hardware circuits

The paper demonstrates that N-ary trees (N>2) can efficiently be used to model and process data in hardware. It is done through: 1) representation of data by N-ary trees; 2) compact coding of N-ary trees in memory; 3) common methods for data processing based on the model of a hierarchical finite state machine (HFSM). The proposed techniques have the following advantages: 1) similarity of processing N-ary trees with different characteristics such as the size of data M, the value N, and the depth d of trees; 2) fixed number of processing steps from the root to leaves for the given depth d; 3) the ease of reconfiguration (customization) of HFSM for different values of N, d, and M; 4) potential parallel processing of nodes' children. The results of experiments confirm effectiveness of the proposed techniques and their applicability for solving practical problems.