论文信息 - Analyzing sigma-delta ADCs in deep-submicron CMOS technologies

Analyzing sigma-delta ADCs in deep-submicron CMOS technologies

Sigma-delta (SD) analog-to-digital-converters are critical components in wireless transceivers. This study shows that a continuous-time, single-loop, single-bit SD ADC is suitable for wireless applications demanding less than 5 MHz conversion bandwidth (GSM Bluetooth, W-CDMA, etc.). On the other hand, for applications that require bandwidth conversion higher than 5 MHz (WLAN), the use of a CT single-loop, multibit SD ADC is recommended.

Yann Le Guillou | Y. L. Guillou

[1] R. Schreier,et al. Delta-sigma data converters : theory, design, and simulation , 1997 .

[2] R. Schreier,et al. Mismatch shaping for a current-mode multibit delta-sigma DAC , 1999, IEEE J. Solid State Circuits.

[3] L. Longo,et al. A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio , 2000, IEEE Journal of Solid-State Circuits.

[4] R. V. Veldhoven. A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003, IEEE J. Solid State Circuits.

[5] Chuan Yi Tang,et al. A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[6] L. R. Carley,et al. A 16-bit 4'th order noise-shaping D/A converter , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[7] W. Sansen,et al. A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC , 2000, IEEE Journal of Solid-State Circuits.

[8] W. Redman-White,et al. Integrated Continuous-Time Balanced Filters for 16-Bit DSP Interfaces , 1992, ESSCIRC '92: Eighteenth European Solid-State Circuits conference.

[9] Michel Steyaert,et al. Optimal parameters for /spl Delta//spl Sigma/ modulator topologies , 1998 .