The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover

We have extended the HOL theorem-prover with an efficient implementation of symbolic trajectory evaluation. Using this extension we can obtain verification results for models of digital hardware — usually with much less effort than would be required using a conventional interactive theorem-proving approach. We illustrate the use of this extension with three examples, namely, the formal verification of a 32-bit adder, an 8-bit by 8-bit multiplier and the MAJORLOGIC block of the Viper microprocessor.