Soft breakdown conduction in ultrathin (3-5 nm) gate dielectrics

Prior to any attempt to model a charge transport mechanism, a precise knowledge of the parameters on which the current depends is essential. In this work, the soft breakdown (SBD) failure mode of ultrathin (3-5 nm) SiO/sub 2/ layers in polysilicon-oxide-semiconductor structures is investigated. This conduction regime is characterized by a large leakage current and by multilevel current fluctuations, both at low applied voltages. In order to obtain a general picture of SBD, room-temperature current-voltage (I-V) measurements have been performed on samples with different gate areas, oxide thicknesses and substrate types. An astounding matching between some of these I-V characteristics has been found. The obtained results and the comparison with the final breakdown regime suggest that the current flow through a SBD spot is largely influenced by its atomic-scale dimensions as occurs in a point contact configuration. Experimental data are also presented which demonstrate that specific current fluctuations can be ascribed to a blocking behavior of unstable SBD conduction channels.

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