Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x

Lateral charge migration and vertical charge detrap degrade the reliability of 3D-Triple-Level Cell (TLC) NAND flash. Lateral charge migration is dominant at the low write/erase (W/E) endurance and vertical charge de-trap is dominant at the high endurance. Conventional techniques address only one of these problems. This paper proposes Endurance-based Dynamic VTHDistribution Shaping (DVDS) to suppress both errors at a wide range of the endurance. At low (1) and high (2k) endurance, measured errors decrease by 27% and 20% and measured acceptable data-retention time increases by 1.7x and 2.7x, respectively.

[1]  Sung-Jin Choi,et al.  Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND flash memory , 2016, 2016 IEEE Symposium on VLSI Technology.

[2]  Xu Li,et al.  A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[3]  Ken Takeuchi,et al.  Lateral charge migration suppression of 3D-NAND flash by vth nearing for near data computing , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[4]  Ken Takeuchi,et al.  Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data , 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

[5]  Byung-Gook Park,et al.  Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[6]  J. Van Houdt,et al.  Impact of lateral charge migration on the retention performance of planar and 3D SONOS devices , 2011, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

[7]  Chih-Yuan Lu,et al.  Cause of data retention loss in a nitride-based localized trapping storage flash memory cell , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[8]  Luca Crippa,et al.  Array Architectures for 3-D NAND Flash Memories , 2017, Proceedings of the IEEE.