Scaled-up Neuromorphic Array Communications Controller (SNACC) for Large-scale Neural Networks

Neuromorphic computing is one promising post-Moore’s law era technology, which takes inspiration from biological brains to perform computing tasks. The human brain contains billions of neurons with trillions of synapses and as neuromorphic hardware systems scale to larger and larger sizes, the communication system used to transfer information between neuromorphic elements and traditional computers must scale to keep up. In prior work, we describe the use of a separate neuromorphic array communications controller to support low-latency, high-throughput communication between our neuromorphic systems and a traditional computer. In this work, the neuromorphic array communications controller is used to support the scaling of a neuromorphic development system which uses multiple neuromorphic processors arranged in a two-dimensional array. The neuromorphic array communications controller, along with scalable local connections, is used to create a scalable neuromorphic platform to enable the development and testing of large neuromorphic network arrays.

[1]  Rodrigo Alvarez-Icaza,et al.  Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations , 2014, Proceedings of the IEEE.

[2]  Dharmendra S. Modha,et al.  A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[3]  Mark E. Dean,et al.  DANNA 2: Dynamic Adaptive Neural Network Arrays , 2018, Proceedings of the International Conference on Neuromorphic Systems.

[4]  Mark E. Dean,et al.  A VLSI Design for Neuromorphic Computing , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[5]  John W. Backus,et al.  Can programming be liberated from the von Neumann style?: a functional style and its algebra of programs , 1978, CACM.

[6]  M. Mitchell Waldrop,et al.  The chips are down for Moore’s law , 2016, Nature.

[7]  Gert Cauwenberghs,et al.  Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain , 2018, Front. Neurosci..

[8]  H. Markram.  The Blue Brain Project , 2006, Nature Reviews Neuroscience.

[9]  Bernard Brezzo,et al.  TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Kwabena Boahen,et al.  A Serial H-Tree Router for Two-Dimensional Arrays , 2018, 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

[11]  Andrew D. Brown,et al.  Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors , 2009, ACSD.

[12]  Catherine D. Schuman,et al.  Biomimetic, Soft-Material Synapse for Neuromorphic Computing: from Device to Network , 2018, 2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS).

[13]  Giacomo Indiveri,et al.  A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs) , 2017, IEEE Transactions on Biomedical Circuits and Systems.

[14]  Patricia Jean Eckhart.  Tiled DANNA: Dynamic Adaptive Neural Network Array Scaled Across Multiple Chips , 2017 .

[15]  Kwabena Boahen,et al.  Braindrop: A Mixed-Signal Neuromorphic Architecture With a Dynamical Systems-Based Programming Model , 2019, Proceedings of the IEEE.

[16]  Catherine D. Schuman,et al.  The TENNLab Exploratory Neuromorphic Computing Framework , 2018, IEEE Letters of the Computer Society.

[17]  Stephan Henker,et al.  A 32 GBit/s communication SoC for a waferscale neuromorphic system , 2012, Integr..

[18]  Hong Wang,et al.  Loihi: A Neuromorphic Manycore Processor with On-Chip Learning , 2018, IEEE Micro.

[19]  Johannes Schemmel,et al.  A wafer-scale neuromorphic hardware system for large-scale neural modeling , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[20]  Aaron Reed Young.  Scalable High-Speed Communications for Neuromorphic Systems , 2017 .

[21]  Stephan Hartmann,et al.  VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality , 2011, Front. Neurosci..

[22]  Alain J. Martin,et al.  Asynchronous Techniques for System-on-Chip Design , 2006, Proceedings of the IEEE.

[23]  Catherine D. Schuman,et al.  An Application Development Platform for neuromorphic computing , 2016, 2016 International Joint Conference on Neural Networks (IJCNN).

[24]  Stephen B. Furber.  Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors , 2009, 2009 Ninth International Conference on Application of Concurrency to System Design.

[25]  Jim D. Garside,et al.  A Programmable Adaptive Router for a GALS Parallel System , 2009, 2009 15th IEEE Symposium on Asynchronous Circuits and Systems.

[26]  James S. Plank,et al.  A Review of Spiking Neuromorphic Hardware Communication Systems , 2019, IEEE Access.

[27]  Catherine D. Schuman,et al.  Design of Superconducting Optoelectronic Networks for Neuromorphic Computing , 2018, 2018 IEEE International Conference on Rebooting Computing (ICRC).

[28]  Frederico A. C. Azevedo,et al.  Equal numbers of neuronal and nonneuronal cells make the human brain an isometrically scaled‐up primate brain , 2009, The Journal of comparative neurology.

[29]  Catherine D. Schuman,et al.  Neuromorphic Array Communications Controller to Support Large-Scale Neural Networks , 2018, 2018 International Joint Conference on Neural Networks (IJCNN).

[30]  Gang Pan,et al.  Darwin: a neuromorphic hardware co-processor based on Spiking Neural Networks , 2015, Science China Information Sciences.