Aliasing-Free Space Compaction in VLSI with Cascade of Two-Input OR/NOR Logic

Designing aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper develops an approach to designing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips for single stuck-line faults, extending well known concept from conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response outputs of the circuit under test, the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other response output pair being simultaneously fault detection compatible) with respect to two-input OR/NOR logic. The process is illustrated with design details of space compactors for the International Symposium on Circuits and Systems or ISCAS 85 combinational (and ISCAS 89 full-scan sequential) benchmark circuits using simulation programs ATALANTA and FSIM, attesting to the importance of the technique from the viewpoint simplicity, resultant low area overhead and full fault coverage for single stuck-line faults, thereby making it an appropriate choice in commercial design environments.

[1]  Wen-Ben Jone,et al.  On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing , 2006, IEEE Transactions on Instrumentation and Measurement.

[2]  Dong Sam Ha,et al.  AN EFFICIENT, FORWARD FAULT SIMULATION ALGORITHM BASED ON THE PARALLEL PATTERN SINGLE FAULT PROPAGAT , 1991, 1991, Proceedings. International Test Conference.

[3]  Wen-Ben Jone,et al.  A novel approach to designing aliasing-free space compactors based on switching theory formulation , 2001, IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188).

[4]  S.R. Das.  Built-in self-testing of VLSI circuits-getting errors to catch themselves , 1991, IEEE Potentials.

[5]  Subrata R. Das,et al.  On a New Approach for Finding All the Modified Cut-Sets in an Incompatibility Graph , 1973, IEEE Transactions on Computers.

[6]  Rochit Rajsuman.  System-On-A-Chip: Design and Test , 2000 .

[7]  Wen-Ben Jone,et al.  Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities , 2001, IEEE Trans. Instrum. Meas..

[8]  Prawat Nagvajara,et al.  Optimal Robust Compression of Test Responses , 1990, IEEE Trans. Computers.

[9]  S. R. Das,et al.  Self-testing of cores-based embedded systems with built-in hardware , 2005 .

[10]  Jacob A. Abraham,et al.  Test Generation for Microprocessors , 1980, IEEE Transactions on Computers.

[11]  Yervant Zorian,et al.  Testing embedded-core based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[12]  Subhasish Mitra,et al.  X-compact: an efficient response compaction technique for test cost reduction , 2002, Proceedings. International Test Conference.

[13]  Krishnendu Chakrabarty.  SOC (System-on-a-Chip) Testing for Plug and Play Test Automation , 2011 .

[14]  Yervant Zorian,et al.  Principles of testing electronic systems , 2000 .

[15]  R. Daniels,et al.  Built-In Self-Test Trends in Motorola Microprocessors , 1985, IEEE Design & Test of Computers.

[16]  Sunil R. Das.  Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware , 2005, IEEE Transactions on Instrumentation and Measurement.

[17]  Sudhakar M. Reddy,et al.  Convolutional compaction of test responses , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[18]  Sunil R. Das,et al.  Test Response Compaction in VLSI BIST with Array of Two-Input Linear Logic , 2011 .

[19]  John R. Kuban,et al.  Self-Testing the Motorola MC6804P2 , 1984, IEEE Design & Test of Computers.

[20]  Sarita Thakar,et al.  On the generation of test patterns for combinational circuits , 1993 .

[21]  Edward McCluskey,et al.  Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.

[22]  Thomas W. Williams,et al.  Testing Logic Networks and Designing for Testability , 1979, Computer.

[23]  Emil M. Petriu,et al.  Space Compactor Design in VLSI Circuits Based on Graph Theoretic Concepts , 2005, IMTC 2005.