Investigation of CMOS technology for 60-GHz applications

This paper investigates the feasibility of the latest CMOS technology for the implementation of the emerging 60-GHz wireless applications. The double-conversion zero-IF receiver architecture is proposed for the evaluation. From the recently reported work of wireless front-end building blocks, most of the components required in the proposed 60-GHz receiver have been demonstrated in CMOS technology. It is very promising that the improved characteristics of the scaled CMOS technology, down to 0.13 /spl mu/m or below, are viable for the 60-GHz wireless front-end ICs.

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