Analog-digital design in submicrometric digital CMOS technologies

Advanced digital CMOS technologies are poised to become an increasingly important manufacturing platform for mixed analog-digital integrated circuits. This requires that appropriate design methodologies are devised to overcome the main problems facing the design of high performance analog cells. This paper presents an overview of some of those methodologies, giving special emphasis to combined analog and digital circuit solutions for the enhanced performance of the former with little extra cost of the latter. These are discussed in the practical examples of a self-calibrated 300 /spl mu/W, 40 MHz comparator achieving 1 mV resolution, a full 12-bit MOSFET-only /spl Delta//spl Sigma/ modulator, an alternative /spl Delta//spl Sigma/ modulator architecture with minimized analog content, and finally a low offset I/Q D/A interface system.

[1]  J. H. Atherton,et al.  An offset reduction technique for use with CMOS integrated comparators and amplifiers , 1992 .

[2]  C. Azeredo Leme,et al.  Architectures for A/D conversion with optimal use of oversampling , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[3]  John B. Hughes,et al.  S/sup 2/I: a two-step approach to switched-currents , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[4]  A. T. Behr,et al.  Harmonic distortion caused by capacitors implemented with MOSFET gates , 1992 .

[5]  J. E. Franca,et al.  A Full 12-Bit Switched-Current ΔΣ Modulator with Self-Calibration , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

[6]  Eric A. Vittoz The Design of High-Performance Analog Circuits on Digital CMOS Chips , 1985 .

[7]  Gordon W. Roberts,et al.  A comparison of first and second-generation switched-current cells , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[8]  Bernhard E. Boser,et al.  The design of sigma-delta modulation analog-to-digital converters , 1988 .

[9]  Gabor C. Temes,et al.  High-linearity switched-capacitor circuits in digital CMOS technology , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[10]  Behzad Razavi,et al.  Design techniques for high-speed, high-resolution comparators , 1992 .

[11]  J.C.M. Bermudez,et al.  Linearity of switched capacitor filters employing nonlinear capacitors , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[12]  C. Azeredo Leme,et al.  A Low-Power High-Speed Self-Calibrated Differential Comparator , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[13]  J. E. Franca,et al.  A 10 bit low-power CMOS D/A converter with on-chip gain error compensation , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[14]  Gabor C. Temes,et al.  Novel high-frequency track-and-hold stages with offset and gain compensation , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.