Ultralow-Latency Hardware-in-the-Loop Platform for Rapid Validation of Power Electronics Designs

This paper introduces a unified approach to the validation of power-electronics (PE) control hardware, firmware, and software designs. It is based on a scalable application-specific ultralow-latency (ULL) digital processor core. The proposed ULL processor core simulates PE converters and systems comprising multiple power converters with a fixed 1-μs simulation time step and latency, regardless of the size of the system. Owing to its ULL, the proposed platform enables the fully automatic testing and validation of the complete PE design comprising component safe-operating-area validation, system protection, firmware, and software implementation as well as overall system performance optimization.

[1]  Karl S. Hemmert,et al.  Closing the gap: CPU and FPGA trends in sustainable floating-point BLAS performance , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[2]  Haibo Wang,et al.  Self-addressable memory-based FSM: a scalable intrusion detection engine , 2009, IEEE Network.

[3]  Dennis W. Prather,et al.  Floating-Point Accumulation Circuit for Matrix Applications , 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[4]  Steffen Rülke,et al.  A low-cost realization of an adaptable protocol processing unit , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[5]  Kai Strunz,et al.  Nested Fast and Simultaneous Solution for Time-Domain Simulation of Integrative Power-Electric and Electronic Systems , 2007 .

[6]  Chin-Tau A. Lea,et al.  A Programmable State Machine Architecture for Packet Processing , 2003, IEEE Micro.

[7]  Walter Schumacher,et al.  A High-Performance Electronic Hardware-in-the-Loop Drive–Load Simulation Using a Linear Inverter (LinVerter) , 2010, IEEE Transactions on Industrial Electronics.

[8]  Florent de Dinechin,et al.  An FPGA-specific approach to floating-point accumulation and sum-of-products , 2008, 2008 International Conference on Field-Programmable Technology.

[9]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[10]  Jean Belanger,et al.  eMEGAsim: An Open High-Performance Distributed Real-Time Power Grid Simulator. Architecture and Specification , 2007 .

[11]  Wilsun Xu,et al.  Algorithms for the accounting of multiple switching events in digital simulation of power-electronic systems , 2005, IEEE Transactions on Power Delivery.

[12]  V. Dinavahi,et al.  Real-Time Digital Hardware Simulation of Power Electronics and Drives , 2007, 2007 IEEE Power Engineering Society General Meeting.

[13]  Venkata Dinavahi,et al.  Hardware-in-the-Loop Simulation of Power Electronic Systems Using Adaptive Discretization , 2010, IEEE Transactions on Industrial Electronics.

[14]  Larry Owens,et al.  Vannevar Bush and the Differential Analyzer: The Text and Context of an Early Computer , 1991 .

[15]  Salvatore D'Arco,et al.  Comparing the Dynamic Performances of Power Hardware-in-the-Loop Interfaces , 2010, IEEE Transactions on Industrial Electronics.

[16]  Reinhard Männer,et al.  Perspectives for the Use of Field Programmable Gate Arrays for Finite Element Computations , 2005 .

[17]  Thierry Meynard,et al.  Design of FPGA-based emulator for series multicell converters using co-simulation tools , 2003 .

[18]  C. Graf,et al.  Real-time HIL-simulation of power electronics , 2008, 2008 34th Annual Conference of IEEE Industrial Electronics.

[19]  Yerramreddy Srinivasa Rao,et al.  Real-Time Electrical Load Emulator Using Optimal Feedback Control Technique , 2010, IEEE Transactions on Industrial Electronics.

[20]  Michael Steurer,et al.  A Megawatt-Scale Power Hardware-in-the-Loop Simulation Setup for Motor Drives , 2010, IEEE Transactions on Industrial Electronics.

[21]  Mazana Armstrong,et al.  Multilevel MATE for efficient simultaneous solution of control systems and nonlinearities in the OVNI simulator , 2006, IEEE Transactions on Power Systems.

[22]  André DeHon,et al.  Floating-point sparse matrix-vector multiply for FPGAs , 2005, FPGA '05.

[23]  Subhashish Bhattacharya,et al.  Controller hardware-in-the-loop validation for a 10 MVA ETO-based STATCOM for wind farm application , 2009, 2009 IEEE Energy Conversion Congress and Exposition.

[24]  Arun Paidimarri,et al.  FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation , 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

[25]  Guido D. Salvucci,et al.  Ieee standard for binary floating-point arithmetic , 1985 .

[26]  Aleksandar Kovacevic,et al.  Computer Based Emulation of Power Electronics Hardware , 2009, 2009 First IEEE Eastern European Conference on the Engineering of Computer Based Systems.

[27]  S. J. Levine,et al.  An Analysis of the Induction Motor , 1935, Transactions of the American Institute of Electrical Engineers.

[28]  Mi Lu,et al.  Group-Alignment based Accurate Floating-Point Summation on FPGAs , 2006, ERSA.

[29]  Yao Sun,et al.  Carrier modulation of four-leg matrix converter based on FPGA , 2008, 2008 International Conference on Electrical Machines and Systems.

[30]  Viktor K. Prasanna,et al.  High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs , 2007, IEEE Transactions on Parallel and Distributed Systems.

[31]  M.L. Liou,et al.  Computer-aided analysis of electronic circuits: Algorithms and computational techniques , 1977, Proceedings of the IEEE.

[32]  H. C. Stanley.  An Analysis of the Induction Machine , 1938, Transactions of the American Institute of Electrical Engineers.

[33]  Joseph Zambreno,et al.  A floating-point accumulator for FPGA-based high performance computing applications , 2009, 2009 International Conference on Field-Programmable Technology.

[34]  Dragan Maksimovic,et al.  A method for fast time-domain simulation of networks with switches , 1994 .

[35]  C. Dufour,et al.  A PC-based hardware-in-the-loop simulator for the integration testing of modern train and ship propulsion systems , 2008, 2008 IEEE Power Electronics Specialists Conference.

[36]  C. Dufour,et al.  Real-time HIL simulation of a complete PMSM drive at 10 /spl mu/s time step , 2005, 2005 European Conference on Power Electronics and Applications.

[37]  S. Abourida,et al.  REAL-TIME PLATFORM FOR THE CONTROL PROTOTYPING AND SIMULATION OF POWER ELECTRONICS AND MOTOR DRIVES , 2008 .

[38]  Philippe Delarue,et al.  Reduced-Scale-Power Hardware-in-the-Loop Simulation of an Innovative Subway , 2010, IEEE Transactions on Industrial Electronics.

[39]  J. H. Alimeling,et al.  PLECS-piece-wise linear electrical circuit simulation for Simulink , 1999, Proceedings of the IEEE 1999 International Conference on Power Electronics and Drive Systems. PEDS'99 (Cat. No.99TH8475).

[40]  Venkata Dinavahi,et al.  FPGA-Based Real-Time Emulation of Power Electronic Systems With Detailed Representation of Device Characteristics , 2011, IEEE Transactions on Industrial Electronics.

[41]  C. Dufour,et al.  FPGA-Based Real-Time Simulation of Finite-Element Analysis Permanent Magnet Synchronous Machine Drives , 2007, 2007 IEEE Power Electronics Specialists Conference.

[42]  Siegfried M. Rump,et al.  Accurate Sum and Dot Product , 2005, SIAM J. Sci. Comput..

[43]  Dirk Westermann,et al.  A Real-Time Development Platform for the Next Generation of Power System Control Functions , 2010, IEEE Transactions on Industrial Electronics.

[44]  J.G. Kassakian.  Simulating power electronic systems—A new approach , 1979, Proceedings of the IEEE.

[45]  Scott D. Sudhoff,et al.  Analysis of Electric Machinery and Drive Systems , 1995 .