A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology

This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8 V, 0.18 mum digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3 ps peak-to-peak) chip-level clock distribution is ensured by five-level balanced clock tree, implemented in low swing current-mode logic. The ADC block achieves a peak SFDR of 71.3 dB and 9.26 ENOB at 230 MS/s, with an input signal swing of 1.5 Vpp. The measured peak SFDR at 200 MS/s is 78 dB, while the peak SNDR at 200 MS/s is 59.5 dB. The SFDR and SNDR performance exhibits very flat characteristics, maintaining higher than 53 dB SNDR at 230 MS/s and higher than 58 dB SNDR at 200 MS/s, from DC through Nyquist rate input frequencies.

[1]  Ying-Hsi Lin,et al.  An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  Seung-Chul Lee,et al.  A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  Ying-Hsi Lin,et al.  A 10b 200MS/s pipelined folding ADC with offset calibration , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[4]  Kari Halonen,et al.  A digital self-calibration method for pipeline A/D converters , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[5]  Anders Vinje,et al.  A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13μm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  Seung-Hoon Lee,et al.  A 10 b 200 MS/s 1.8 mm2 83 mW 0.13µm CMOS ADC Based on Highly Linear Integrated Capacitors , 2007, IEICE Trans. Electron..

[7]  J. Li,et al.  A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[8]  Qiuting Huang,et al.  A 1.2V 200-MS/s 10-bit folding and interpolating ADC in 0.13-μm CMOS , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.