Cost and yield analysis of multi-die packaging using 2.5D technology compared to fan-out wafer level packaging

As the market drives electronic products to be smaller and faster, designers must use advanced packaging technologies. In many cases, these technologies are significantly more expensive than traditional packaging, but are necessary to meet the product requirements. Both fan-out wafer level packaging and 2.5D packaging on a silicon interposer enable designers to package multiple die in close proximity. This close proximity helps achieve miniaturization and may enable better performance since die to die interconnect is shorter. However, care must be taken to manage the total cost and yield of the system. Both of these technologies have the potential to meet the smaller and faster market requirement, but if either is used on the wrong design, the cost can be high and the yield can be low. In this paper we will compare and contrast the packaging cost drivers for multi-die fan-out wafer level packaging and 2.5D packaging on a silicon interposer. Total cost and yield plus individual activity costs and yields will be presented across a range of design characteristics including package size, die size, number of die, and number of IOs. An in depth analysis of the cost of cumulative yield loss will be presented for both technologies. A sensitivity analysis on key cost and yield drivers will also be presented in the paper.