A 1 V 6-bit 2.4 GS/s Nyquist CMOS DAC for UWB systems

A 6-bit 2.4 GS/s current-steering DAC fabricated in a 65 nm CMOS technology for ultra-wideband (UWB) systems is presented. The prototype achieves a measured spurious-free dynamic range (SFDR) of more than 36 dB over the Nyquist bandwidth at 2.4 GS/s. Among the 50 measured samples, DNL/INL of 0.02/0.02 LSB was the lowest achievable value. The DAC core occupies an area of merely 0.023 mm2 through simplified circuit and careful layout. To operate from a relatively low analog power supply of 1 V, a portion of current cell is implemented using low threshold voltage devices. Total maximum power consumption, including the low voltage differential signaling (LVDS) stage, is 14 mW at 2.4 GS/s.

[1]  W. Sansen,et al.  A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[2]  Day-Uei Li,et al.  1 V 1.25 GS/s 8 mW D/A Converters for MB-OFDM UWB Transceivers , 2007, 2007 IEEE International Conference on Ultra-Wideband.

[3]  M. Steyaert,et al.  A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC , 2007, IEEE Journal of Solid-State Circuits.

[4]  Michiel Steyaert,et al.  An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters , 2001 .

[5]  Tao Chen,et al.  The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Michiel Steyaert,et al.  A 130 nm CMOS 6-bit full nyquist 3GS/s DAC , 2007, 2007 IEEE Asian Solid-State Circuits Conference.

[7]  Tao Chen,et al.  The Analysis and Improvement of a Current-Steering DAC's Dynamic SFDR—II: The Output-Dependent Delay Differences , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Soon-Jyh Chang,et al.  A 5-bit 1.35-GSPS DAC for UWB transceivers , 2009, 2009 IEEE International Conference on Ultra-Wideband.