论文信息 - Tamper Resistivity Analysis for Nano-meter LSI with Process Variations

Tamper Resistivity Analysis for Nano-meter LSI with Process Variations

We have studied tamper resistivity with process variations. We have established a simulation platform to evaluate target LSI with differential electro-magnetic analysis. We have shown that wave dynamic differential logic (WDDL) becomes weak in terms of process variation. Based on the simulation platform, we have demonstrated several design styles including short wire, wire segmentation, and 3-wire, 3-phase systems.

Makoto Ikeda | Kunihiro Asada | Hiroshi Yamauchi

[1] Bruce Schneier,et al. Side channel cryptanalysis of product ciphers , 2000 .

[2] Ingrid Verbauwhede,et al. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[3] M. Ikeda,et al. Analysis of low noise three-phase asynchronous data transmission , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[4] Patrick Schaumont,et al. A side-channel leakage free coprocessor IC in 0.18/spl mu/m CMOS for embedded AES-based cryptographic and biometric processing , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[5] Paul C. Kocher,et al. Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems , 1996, CRYPTO.

[6] Jean-Jacques Quisquater,et al. A Practical Implementation of the Timing Attack , 1998, CARDIS.

[7] Francis Olivier,et al. Electromagnetic Analysis: Concrete Results , 2001, CHES.