Design for ASIC reliability for low-temperature applications

A design for reliability methodology has been developed for electronics for low-temperature applications. A hot carrier aging (HCA) lifetime projection model is proposed to take into account the HCA impact on technology, analysis of parametric degradation versus critical circuit path degradation, transistor bias profile, transistor substrate current profile, and operating temperature profile. The most applicable transistor size can be determined in order to meet the reliability requirements of the electronics operating under low temperatures. This methodology and approach can also be applied to other transistor-level failure and/or degradation mechanisms for applications with varying temperature ranges

[1]  G. Ghibaudo,et al.  Device and circuit cryogenic operation for low-temperature electronics [Book Review] , 2002, IEEE Circuits and Devices Magazine.

[2]  E. Xiao.  A design technique to reduce hot carrier effect , 2003, IEEE International Integrated Reliability Workshop Final Report, 2003.

[3]  Chenming Hu,et al.  The effects of hot-electron degradation on analog MOSFET performance , 1990, International Technical Digest on Electron Devices.

[4]  P. K. Ko,et al.  A New Insight Into Correlation Between DC And AC Hot-carrier Degradation Of MOS Devices , 1993, Symposium 1993 on VLSI Technology.

[5]  K. Hess,et al.  Improvement of hot carrier reliability with deuterium anneals for manufacturing multilevel metal/dielectric MOS systems , 1998, IEEE Electron Device Letters.

[6]  R.L. Anderson,et al.  Hot-electron-induced interface state generation in n-channel MOSFET's at 77 K , 1987, IEEE Transactions on Electron Devices.

[7]  Hai Wang,et al.  Analyzing hot-carrier effects on cold CMOS devices , 1987, IEEE Transactions on Electron Devices.

[8]  W. Jungling,et al.  Suppression of hot-carrier effects in submicrometer CMOS technology , 1988 .

[9]  Chenming Hu,et al.  Prediction of hot-carrier degradation in digital CMOS VLSI by timing simulation , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[10]  A. Acovic,et al.  A study of the increased effects of hot-carrier stress on NMOSFETs at low temperature , 1989 .

[11]  Jason C. S. Woo,et al.  Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K , 1997 .

[12]  Malgorzata Marek-Sadowska,et al.  Layout-driven hot-carrier degradation minimization using logic restructuring techniques , 2001, DAC '01.

[13]  Steven W. Mittl,et al.  Doping profile design for substrate hot carrier reliability in deep submicron field effect transistors , 1991, 29th Annual Proceedings Reliability Physics 1991.

[14]  Miryeong Song,et al.  New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures , 1997, 1997 IEEE International Reliability Physics Symposium Proceedings. 35th Annual.

[15]  Wei-Jen Huang,et al.  Hot-carrier reliability design guidelines for CMOS logic circuits , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[16]  Eric A. Vittoz.  The Design of High-Performance Analog Circuits on Digital CMOS Chips , 1985 .