Design and Reliability Analysis of a Class of Irregular Fault-tolerant Multistage Interconnection Networks

llel processing can be used to design high performance computing systems. In a parallel computer inter-connecting processors and linking them efficiently to the memory modules is not an easy task. Therefore, there is a requirement of an interconnection network that provides the desired connectivity and performance at minimum cost. Multistage interconnection networks (MINs) provide cost-effective, high- bandwidth communication between processors and/or memory modules in comparison to bus and crossbar interconnection networks. In this paper a new irregular MIN named IFTN (Improved Four Tree Network) has been proposed. The performance of IFTN has been measured in terms of reliability and cost. It has been proved that the proposed network IFTN provides much better fault-tolerance and reliability at lesser cost In Comparison To Four Trees.

[1]  Chen Zhen,et al.  Balance routing traffic in Generalized Shuffle-Exchange Network , 2005 .

[2]  A. Himanshu,et al.  Routing and path length algorithm for cost effective modified four tree network , 2002, 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. TENCOM '02. Proceedings..

[3]  Dharma P. Agrawal,et al.  Performance of multiprocessor interconnection networks , 1989, Computer.

[4]  Yulu Yang,et al.  Super recursive baselines: a family of new interconnection networks with high performance/cost ratios , 2000, Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN 2000.

[5]  Sandeep Sharma,et al.  On a Class of Multistage Interconnection Networks in Parallel Processing , 2011 .

[6]  E.V. Prasad,et al.  Permutation Capability and Connectivity of Enhanced Multistage Interconnection Network(E-MIN) , 2006, 2006 International Conference on Advanced Computing and Communications.

[7]  Sung-Kwan Youm,et al.  A heuristic multi-path routing scheme for online traffic in MPLS networks , 2010, Comput. Syst. Sci. Eng..

[8]  Dharma P. Agrawal,et al.  A Survey and Comparision of Fault-Tolerant Multistage Interconnection Networks , 1987, Computer.

[9]  Hu Chen,et al.  A Parallel Shortest Path Algorithm Based on Graph-Partitioning and Iterative Correcting , 2008, 2008 10th IEEE International Conference on High Performance Computing and Communications.

[10]  Kuldip Singh,et al.  Routing and path length algorithm for a cost-effective four-tree multistage interconnection network , 1992 .

[11]  Jyotsna Sengupta,et al.  Permutation and reliability measures of regular and irregular MINs , 2000, 2000 TENCON Proceedings. Intelligent Systems and Technologies for the New Millennium (Cat. No.00CH37119).

[12]  Kuldip Singh,et al.  Fault-Tolerant Augmented Baseline Multistage Interconnection Network , 1991, TENCON '91. Region 10 International Conference on EC3-Energy, Computer, Communication and Control Systems.

[13]  Jyotsna Sengupta,et al.  High speed dynamic fault-tolerance , 2001, Proceedings of IEEE Region 10 International Conference on Electrical and Electronic Technology. TENCON 2001 (Cat. No.01CH37239).

[14]  Nitin.  On Analytic Bounds of Regular and Irregular Fault-Tolerant Multi-Stage Interconnection Networks , 2006, PDPTA.