A 5‐ns 32 K ×8/×9 bi‐CMOS TTL SRAM with alternated bit line load architecture

An ultrahigh-speed 32 K ×8/×9 TTL bi-CMOS SRAM with a 5-ns standard access time was developed using a five-layer polysilicon/two-layer aluminum 0.6-μm bi-CMOS process with 4.2 × 5.6-μm2 4-M SRAM-class small-size memory cells, ultrahigh capacity, self-aligned bipolar electrodes with 18.5-GHz cutoff frequency and 0.6-μm/0.7-μm (nMOS/pMOS) gate-length MOS transistors. This fast access time was achieved by using center power pin-out to reduce output noise, a major problem in the TTL SRAM, together with alternated bit line load architecture, a memory array architecture well suited to center power pin-out. Also used were a bit-line load circuit for rapid precharging of the bit line and a high-speed wired-OR column-sensing circuit.

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