Thermal protection of an 80V silicon-on-insulator LDMOS transistor for power-over-Ethernet applications

This paper describes thermal protection for the pass transistor of a power-over-Ethernet powered device controller developed on a bonded-wafer silicon-on-insulator process. The 1/spl Omega/, 80V LDMOS transistor dissipates up to 8W during a typical fault condition. Current limiting, tightly coupled over-temperature sensing, and drain-to-source voltage sensing combine to limit measured peak junction temperatures to less than 250/spl deg/C.

[1]  Taylor R. Efland,et al.  Robust 80 V LDMOS and 100 V DECMOS in a streamlined SOI technology for analog power applications , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.

[2]  Philip L. Hower,et al.  Using "Adaptive resurf" to improve the SOA of LDMOS transistors , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[3]  R. J. Widlar,et al.  Dynamic safe-area protection for power transistors employs peak-temperature limiting , 1987 .